1. Field of the Invention
The present invention relates to DRAMs, and more specifically to a method and a device enabling increasing the refreshment voltage of the cells in a DRAM.
2. Discussion of the Related Art
A DRAM includes memory cells in which a logic information xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d can be stored. Each memory cell includes a capacitor in which a predetermined voltage chosen from among two values is stored according to whether a 1 or a 0 is memorized in the cell. The capacitor of a memory cell can never be perfectly isolated, and the voltage on the capacitor is not steady and declines along time. After a predetermined duration, called the retention period, the voltage stored in the capacitor of a memory cell may thus be too small to be readable. To avoid loss of the information stored in each capacitor, the voltage stored in each capacitor is periodically refreshed. For this purpose, a read device periodically compares the voltage stored in each capacitor with a reference voltage, after which it charges each capacitor to one or the other of the predetermined voltages according to whether the compared voltage is greater or smaller than the reference voltage.
FIG. 1 schematically shows a conventional DRAM structure arranged in rows and columns. A single memory cell Mi of the memory is shown. Memory cell Mi includes a capacitor Ci having a first terminal connected to a reference voltage Vp. A second terminal of capacitor Ci is connected to a bit line BL via a switch Si. The second terminal of capacitor Ci forms an input/output terminal of memory cell Mi. The control terminal of switch Si forms a terminal of selection of memory cell Mi, and receives a selection signal WLi. Bit line BL is connected to an input terminal of a read device 2 via a switch 4. Device 2 includes two identical inverters 6 and 8 assembled in antiparallel. Input I6 of inverter 6, connected to the output of inverter 8, forms the input terminal of device 2. The output of inverter 6 is connected to input I8 of inverter 8. A high supply terminal of inverters 6 and 8 is connected to a positive supply voltage Vdd via a switch 10. Switch 10 receives a control signal RESTORE. A low supply terminal of inverters 6 and 8 is connected to a ground voltage GND via a switch 12. Switch 12 receives a control signal SENSE. The input of inverter 8 is connected to a reference bit line BLref via a switch 14. Switches 4 and 14 receive a same control signal PASS. Reference bit line BLref is provided to exhibit a stray capacitance identical to that of bit line BL. A reference memory cell Mref, having a structure identical to that of memory cell M, is connected to reference bit line BLref. Cell Mref includes a capacitor Cref connected to bit line BLref via a switch Sref. Capacitor Cref is identical to capacitor Ci. The terminal of selection of memory cell Mref receives a control signal WLref. A precharge circuit 16, controlled by a signal PRA, is connected to terminals I6 and I8. Precharge circuits, not shown, controlled by signal PRA, are connected to lines BL and BLref and to the input/output terminal of memory cell Mref. Control signals WLi, WLref, PASS, RESTORE, and PRA are generated by control means not shown.
Bit lines BL and BLref are connected to a refreshment device 18. Device 18 includes P-channel MOS transistors 20 and 22, having their respective drains connected to lines BL and BLref. The sources of transistors 20 and 22 are interconnected. The gate of transistor 20 is connected to the drain of transistor 22 and the gate of transistor 22 is connected to the drain of transistor 20. A P-channel transistor 24 has its source connected to a supply voltage Vcc greater than voltage Vdd and its drain connected to the sources of transistors 20 and 22. The gate of transistor 24 receives a control signal noBOOST.
FIGS. 2A through 2H illustrates the variation along time of the voltages of bit lines BL and BLref, and of signals WLi, WLref, SENSE, RESTORE, PASS, noBOOST, and PRA in a step of refreshment of memory cell Mi. At an initial time t0, signals WLi and WLref are at 0 and capacitors Ci and Cref of memory cells Mi and Mref are isolated from lines BL and BLref. Signal PASS is at 0 and terminals I6 and I8 are isolated from lines BL and BLref. Signals SENSE and RESTORE are at 0 and inverters 6 and 8 are deactivated. Signal PRA is at 1 and block 16 forces the voltages of terminals I6 and I8 to a voltage Vdd/2. Similarly, precharge circuits, not shown, force bit lines BL and BLref to voltage Vdd/2, and the input/output terminal of cell Mref to a reference voltage which is considered, for simplification, to be equal to Vdd/2.
At a time t1, signal PRA is brought to 0. The precharge circuits are then deactivated.
At a time t2, signals WLi, WLref, and PASS are brought to 1. Capacitors Ci and Cref are then respectively connected to terminals I6 and I8. Bit line BL and terminal I6 each exhibit a mainly capacitive predetermined impedance. From time t2, the charges stored in capacitor Ci distribute between capacitor Ci and the stray capacitances of line BL, of terminal I6, and of the gate of transistor 22. FIG. 2 illustrates an example in which a voltage Vdd/2+xcex94V is stored in capacitor Ci at a time t2. After time t2, the charges stored in capacitor Ci distribute between capacitor Ci and the stray capacitances of bit line BL, of terminal I6, and of the gate of transistor 22. Because of the charge transferred to the stray capacitances, the terminal I6 is thus brought to a voltage Vdd/2+xcex4V smaller than voltage Vdd/2+xcex94V. Terminal I8, connected to line BLref and to capacitor Cref, remains at voltage Vdd/2.
At a time t3, signal SENSE is brought to 1 to turn switch 12 on. The low supply terminals of inverters 6 and 8 are then connected to voltage GND. As a response to voltage Vdd/2+xcex4V of terminal I6, inverter 6 forces terminal I8 and line BLref to voltage GND.
At a time t4, signal RESTORE is brought to 1 to turn switch 10 on. Inverters 6 and 8 are then supplied by voltage Vdd, and inverter 8 forces terminal I6 and line BL to voltage Vdd. Memory cell Mi is then recharged to voltage Vdd. Technological progress and the increase in memory circuit integration especially causes a reduction in the size of the transistors (not shown) forming inverters 6 and 8, and a decrease in supply voltage Vdd of these transistors. Now, a memory cell refreshed with too small a voltage Vdd is rapidly discharged, that is, it soon becomes unable to provide a sufficient voltage Vdd/2+xcex94V to control inverter 6 at time t3. Device 18 is provided to pull up the refreshment voltage of memory cell Mi.
At a time t5, signal noBOOST is brought to 0 to turn switch 24 on. Their transistors 20 and 22 must be matched so that their characteristics are identical and remain so, for example, in case of a variation in the operating temperature. In the example shown, the gate-source voltage of transistor 20 is more negative than the gate-source voltage of transistor 22 and transistor 20 becomes more conductive than transistor 22. As a result, from time t5, line BL is quickly brought to voltage Vcc, which results in turning transistor 22 off. Line BLref thus remains at voltage GND. Memory cell Mi is then recharged to voltage Vcc, and the refreshment operation is over.
At a time t6, signal noBOOST is brought to 1 to make transistor 24 non-conductive and deactivate device 18. At time t6, signal PASS is brought to 0, to turn off switches 4 and 14 and to isolate terminals I6 and I8 from lines BL and BLref, respectively. At time t6, signals SENSE and RESTORE are brought to 0 to turn off switches 10 and 12 and to deactivate inverters 6 and 8. At time t6, signals WLi and WLref are brought to 0 to isolate capacitors Ci and Cref from lines BL and BLref.
At a time t7, precharge signal PRA is brought to 1 to control the precharge of terminals I6 and I8, of lines BL and BLref, and of capacitor Cref, to prepare a next refreshment operation.
In the illustrated example, memory cell Mi stores before time t2 a voltage Vdd/2+xcex94V (logic xe2x80x9c1xe2x80x9d) greater than voltage Vdd/2 stored in reference memory cell Mref. In the case where memory cell Mi stores a voltage (logic xe2x80x9c0xe2x80x9d) smaller than the voltage stored in cell Mref, device 2 brings line BL to voltage GND at time t3 and line BLref to voltage Vdd at time t4. At time t5, device 18 then brings bit line BLref to voltage Vcc and maintains line BL at voltage GND.
A read operation on memory cells Mi includes the refreshment operation just described. The result of the read operation is for example indicated by the state of terminal I6 at time t5. For a write operation on cell Mi, a means not shown forces the state of terminal I6 before activating device 18, whatever the voltage stored in capacitor Ci.
Matched transistors 20 and 22 must have a large gate length to be able to undergo high voltages, and a large gate width, to be able to rapidly switch when switched, at time t6. The gate connections of transistors 20 and 22 must have the same lengths for transistors 20 and 22 to switch under the same conditions. In practice, the implantation of matched transistors 20 and 22 is particularly difficult and a significant surface area is reserved in the extension of each pair of memory cell columns to adequately arrange these transistors. A mismatching is likely to cause a switching failure and a read error.
Further, voltage Vdd/2+xcex4V provided to inverter 6 from voltage Vdd/2+xcex94V stored in the memory cell is all the smaller as the gate capacitance of transistor 22 is strong.
An embodiment of the present invention provides a device for refreshing bit lines of a DRAM, which enables faultless refreshment, without requiring the presence of two perfectly matched transistors.
An embodiment of the present invention provides a method for refreshing the voltage of a circuit line capable of being brought to a ground voltage or to a first voltage, including the successive steps of:
storing a line voltage in a capacitor; and
controlling, by means of the stored voltage, a switch connecting the line to a second voltage of absolute value greater than the first voltage, whereby the line is set to the second voltage if, during the step of storing, the line was at the first voltage.
According to an embodiment of the present invention, the circuit is a DRAM, the line being connected to at least one memory cell of the DRAM, and being likely to be brought to the ground voltage or to the first voltage by a read device of the memory cell.
An embodiment of the present invention is also directed at a circuit for refreshing the voltage of a circuit line initially brought to a ground voltage or to a first voltage, including:
a first switch connecting the line to a second voltage having an absolute value greater than the first voltage;
a capacitor having a first terminal connected to the control terminal of the first switch;
a second switch connecting the line to the first terminal of the capacitor;
a third switch connecting a second terminal of the capacitor to the line;
a fourth switch connecting the second terminal of the capacitor to the ground voltage; and
a control means for, first, turning on the second and fourth switches and turning off the third switch and, second, turning on the third switch and turning off the second and fourth switches.
According to an embodiment of the present invention, the first switch is a first N-channel MOS transistor having its drain and its source respectively connected to the second voltage and to the line, and having its gate connected to the first terminal of the capacitor;
the second switch is a second N-channel MOS transistor having its drain connected to the first terminal of the capacitor and having its source connected to the line;
the third switch is a third N-channel MOS transistor having its drain connected to the second terminal of the capacitor and having its source connected to the line.
According to an embodiment of the present invention, the fourth switch includes a fourth N-channel MOS transistor having its drain connected to the second terminal of the capacitor and having its source connected to the ground voltage.
According to an embodiment of the present invention, the line is connected to a plurality of memory cells of the DRAM, and is likely to be brought to the ground voltage or to the first voltage by a device for reading from the memory cell.
The foregoing features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.